The difference between FireWorld2 and FireWorld with a capital W like in WireWorld is that two red photon/electron cells may be either in a "2a" or "2k" position to give birth next to 2 or 3 wire cells, logically matching the underlying 03ajkr/2ak/3 rule. In Fireworld2 they may only be in the orthogonal 2a position. The newer Izhora 2b computer works with both rules, while the display of the original model relies on a reaction that does not work in FireWorld and requires Fireworld2. There is a variety of FireWorld called FireWorld7, slightly modified by adding S7 (03ajkr7/2ak/3), which turns blocks into cool p3 guns; the computer works identically under this variant and changes of any natural patterns are unlikely. All my further development focuses on FireWorld and machines with a 256x128 display.
It took me about a year to build a computer in Fireworld2. Yesterday it successfully passed some tests and performed its "Hello World" program!
The current basic version, Izhora 1, has 256k of 32-bit word-addressable XOR-writable RAM, a 32-bit accumulator, a 16-bit program counter and a 128x64 graphic display. It has only one operation: a variety of Subleq known to be Turing-complete. On each cycle, the CPU reads a 32-bit word from the RAM and interprets its 16 highest bits and an absolute jump address and the lower 16 bits as an operand address. The accumulator is then subtracted from the operand; the result is stored in both the accumulator and the operand. If the result was zero or negative, the CPU branches to the jump address; otherwise it proceeds to the next instruction.
As simple as it is, Subleq systems are known to be practical. Some guy even wrote a full-fledged OS with a C-like compiler for an emulated 64-bit Subleq computer! Playing with it and with my own emulators of OISC (one instruction set computers) convinced me that Subleq is totally usable, somewhat similar to some real-life machines like PDP-8, although things like arbitrary bit manipulations or multiplication may require loops with hundreds of operations.
The RAM has a NUMA architecture. Cells located close to the CPU are accessed about 4 times faster than the furthest ones. The display memory starts at #0400. Note that since the machine was 32-bit addressing, #100 means 1024, not 256 bytes. The lowest 4k of the memory should be used for common library functions and variables.
The emulator, written in Common Lisp, is currently in pre-alpha stage (usable though). I hope to find time to write a Python as well as, perhaps, a C and Java version. An assembler and scripts for coding the actual machine in Golly are yet to be written. Some work has been already done toward a new version of the computer that will have, hopefully, RISC features implemented by mapping some jump addresses to other operations, optional relative addressing mode, several registers with an advanced ALU, and a script-driven emulated keyboard. If I ever find time for this...
Although the computer is fully operational, each operation takes about 40,000 generations on average. Programs longer than 10-20k will inevitably slow down hashlife. Don't expect to see more than 10 operations per second. The only way to run programs reasonably fast on Golly would be by a custom simulator script yet to be written.
By the way, Izhora is a river in outskirts of St. Petersburg, named after an ancient Finno-Ugric nation indigenous to the area.
Github repository:
https://github.com/yoelmatveyev/Izhora
"Hello World":
https://github.com/yoelmatveyev/Izhora/ ... _world.rle
The RAM uses p3 electron/photon streams and is very compact, approaching the theoretical limit of 1 bit per 6 cells (in practice, about 1 bit per 8 cells, because each 256-byte/64-word segment contains a controller). P6 is used for the CPU, because it can be crossed over with the dense p3 data and because p6 seems to be the minimum for flip-flops used in the adder and subtractor.
Besides the memory, this computer uses only stable asynchronous logic, which largely eliminates the timing issues. Clocks inside various parts turn automatically off after processing a stream of bits. All data outside of the pulsating memory wiring is encoded by a pilot bit indicating an incoming data stream, kind of like in a modem. A single photon means 0, unless it's used in something like a plain toggle flip-flop. Serial logic also eliminates the need for extensive bus wiring.
Some parts used in this project (to play, remove the dots blocking the p6 guns):
32-bit adder:
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x = 303, y = 138, rule = Fireworld2
29$66.C.C.C.C.C.C$79.C$171.C$62.C7.A.A.A4.C61.C29.C6.C3.C.C$62.C16.C
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C$60.C7.A.A.A4.C2$77.C$64.C.C.C.C.C.C!
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x = 296, y = 98, rule = Fireworld2
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31.C7.A.A.A4.C68.C29.C6.C3.C.C$88.C148.C$138.C$125.C.C.C.C.C.C!
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x = 154, y = 87, rule = Fireworld2
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C.C.C.C.C.C3.C$73.13C8.12C3.C$77.C3.C27.C$71.2C4.C3.C10.2C15.C$71.3C
3.C3.C10.3C14.C$71.3C3.C3.C10.3C14.C$67.C5.C4.C2.C6.C5.C14.C$67.C14.C
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C2.C10.C2.C$68.C3.C2.C30.C20.C.C$58.C16.C12.C3.C3.C3.C5.C4.C2.C2.C2.
4C4.3C$55.C2.C6.C2.C2.C.4C10.C3.C3.C3.C4.C.C4.C15.C2.C$58.2C4.C2.C19.
C3.C3.C3.C14.C5.C2.C6.C$55.C2.C13.C4.C.C7.C3.C3.C3.C6.6C3.C5.C.C6.C$
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12C3.C20.C$55.C21.C3.C27.C20.C$55.C15.2C4.C3.C10.2C15.C20.C$55.C15.3C
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2C4.C2.C41.C20.C$11.CA3.C41.C13.C4.C.C10.C18.C20.C$10.2BA42.C2.C15.2C
3.C10.C18.C20.C$11.C46.C10.C13.C21.5C20.C$67.13C4.7C7.C.C3.C25.C$58.C
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24.C$130.C$130.C$130.C$101.C.C26.C$102.C27.C$101.2C27.C$102.29C!
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x = 110, y = 52, rule = Fireworld2
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A17.A9.C$34.2C.C21.C19.C3.C$42.C.2C13.C3.C.2C12.C3.C$49.C.C.C.C.C.C9.
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42.C10.C!
A note about asynchronous logic: unmatched data streams could be easily synchronized by storing them in registers and shooting them out synchronously after receiving all expected streams, thus eliminating timing issues even more. However, this would significantly slow down the computation. My CPU is self-synchronized by the data read from the RAM.
It's also possible to use pulsating logic for things like inverters by using an AND regulator for aligning p6 signals:
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x = 106, y = 70, rule = Fireworld2
10$52.A13.CB$51.B2C.C6.AC4.C2.C$51.C10.BC4.BA$56.BA5.A4.CA$46.C6.11C
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46.C27.C5.C2.C$46.2C18.C11.C$46.C5.2C.C7.C3.AC2.C$46.C4.CA2B8.C2.BA$
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$78.C!
Such a regulator is also used to detect the right moment for accessing the rotating memory segments. It reads p3 sequences from a 6-bit register that read p6 data and converts them to pulsating p3 bytes (with 2 trailing zeros). These bytes are then xored with a clock that produces a constant stream of increasing bytes. When the match is found, another clock initiates an r/w memory cycle. The RAM is in principle byte-accessible and could even be made bit-accessible.
I only use simple regulators for single trigger signals pulsating at p24:
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x = 35, y = 32, rule = Fireworld2
6$26.CA$26.B2C.C3$28.2B.C$28.3A$31.C2$28.A2.C2$25.C$23.3C3.A.C$4.BA$
4.BA17.C.C$28.2C$28.2C2$22.C.2C3$25.2C.C$27.C$28.C$28.C!
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x = 41, y = 41, rule = Fireworld2
4$30.C$31.5C.C$33.AB$35.2B$35.2A11$35.2B$7.C$15.BA10.BA7.A.C$7.C7.BA
10.BA$7.C$6.AC27.2C$6.BC27.2C$7.C$6.C4$35.2B$35.2A5$36.C!
[5-bit column number][5-bit row number][6-bit address of the actual pulsating 32-bit word]
Read/write cycles are triggered when 2 p3 streams of 32 bits, sent to the right column and the right row, match each other inside the RAM grid by an AND gate. AND gates don't work properly with arbitrary p3 data (p4 seems to be the absolute minimum for simple AND gates). Nevertheless, they do work for detecting and receiving 2 identical data streams. The memory requires only XOR, NOT, a temporary lock for filtering out the pilot bit and a simple data extraction mechanism that reads 47-48 bits. The unwanted trailing bits are later cut upon reading the data and converting it into a 32-bit p6 stream. All this works well with p3, as well as the display, although in order to make the pixel detectors smaller I use a crude flip-flop mechanism that produces annoying frame refresh lines on the screen. I would like to improve it, if I find a clean flip-flop of the same or smaller size capable of operating at p3.