dbell wrote: ↑May 19th, 2025, 7:18 am
Here are some more reactions to detect still lifes.
Very nice! I have almost no time to do any work on this topic these days, unfortunately, but I'm very interested in these kinds of reactions. During early discussions of data tapes while inventing the old 2004 prototype Spartan universal constructor, Paul Chapman and I ended up calling these "ND-READ" reactions -- non-destructive read, as distinguished from D-READ (destructive read) where the object representing the bit of data had to be rebuilt after the read.
It seems to have turned out so far that destructive-read memory devices are significantly easier to work with than ND-READ memory. For example, the 1D and 2D memory circuits in modular computer circuitry compiled from APGsembly all have D-READ bits.
(There have been a few experiments with ND-READ memory tapes, like the
replicator designs by Anivec, but I had some trouble figuring out how far along that project got, and what remaining problems needed to be solved.)
I'm thinking D-READ has been implemented more commonly, because an ND-READ system needs a slightly trickier instruction set
READ, RESET (set to 0), SET (set to 1)
-- where at least one of RESET and SET have to work no matter if the existing bit is OFF or ON ... unless a complicated multi-stage mechanism is set up to do
SET-to-0 = (READ; if result == 0 then PASS else RESET)
SET-TO-1 = (READ; if result == 0 then SET else PASS)
By contrast, a destructive-read bit is always reset after a read, so the branch of the code that deals with processing the results of the read can confidently perform a simple SET operation if a 1 has been read and the information needs to be retained.
Looking for a better 2D memory mechanism
There's one big hole in the long-running project to modernize APGsembly-compilable circuitry. Nobody has ever dared to tackle a rework of the "SQ" / "B2D" unit, so it's still the same exact one that appeared in the original 2010 Osqrtlogt unit.
dvgrn wrote: ↑December 14th, 2024, 5:03 pm
... the mechanism that writes and reads bits to the 2D memory array almost certainly needs some
serious optimization. What modern design would have the smallest number of total gliders for all of the salvos that need to be sent -- to INC and DEC the two reading arms, and to produce the reactions that READ and SET a bit at the current location?